SmGen 91 - Download

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About SmGen

SmGen is a finite state machine (FSM) generator for Verilog. On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this...

SmGen is a finite state machine (FSM) generator for Verilog. On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing

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Previous Versions

Here you can find the changelog of SmGen since it was posted on our website on 2015-04-27 03:00:00. The latest version is 91 and it was updated on 2024-04-22 16:07:59. See below the changes in each version.

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Related Apps

Here you can find apps that are similar with SmGen.

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